The present invention relates to the testing of integrated circuitry and, more particularly, to the scan testing of integrated circuitry grouped in modules capable of being used in other integrated circuitry.
The integrated circuitry on a chip is commonly tested. This testing may be associated with design analysis. Moreover, production chips of an integrated circuit design are checked for manufacturing flaws before being furnished to a customer.
The above checking includes applying a test program to the circuitry to determine if logic on the chip will react as desired to various electrical inputs.
The test program may include one or more scan patterns to be applied to the specimen of the circuit to be tested. Scan patterns can typically detect more manufacturing flaws than manually generated test patterns. Scan patterns are usable only on circuits which include particular logic for scanning. These special circuits are called "scanned circuits". In a scanned circuit, some or all of the flip-flops are replaced with scan flip-flops. Additional scan support logic may also be present. A scan flip-flop typically has two modes: a normal operation mode, and a scan test mode. The scan flip-flops and the scan support logic provide an additional method of controlling and observing the circuits' internal values.
A scan pattern includes one or more test sequences which, in turn, include one or more "scan operations". A scan operation is a set of input stimulus which loads specified values into the scan flip-flops (a scan-in operation), or extracts expected values from the scan flip-flops (a scan-out operation). Note that scan-in and scan-out operations can occur simultaneously. During a scan operation, the scan flip-flops are placed into scan test mode, values are loaded and/or extracted from the scan flip-flops, then the scan flip-flops are placed back into normal operation mode. A typical test sequence in a scan pattern consists of a scan-in operation, a set of input stimulus (with the scan flip-flops in normal operation mode), and a scan-out operation.
Each of the scan patterns making up a test program is formed by applying an ATPG (Automated Test Pattern Generation) program and tools to an integrated circuit design having scan flip-flops to develop ATPG patterns. The ATPG program takes advantage of the presence of the scan flip-flops by loading desired values into the scan flip-flops or by specifying expected values that should be extracted from such scan flip-flops. A translator program converts the ATPG pattern into a scan pattern designed for the circuitry to be tested.
In the basic implementation of scan, a design is tested as one entity, and the design's scan flip-flops are interconnected into a single, long shift register (a scan chain). Values are loaded and/or extracted from the scan flip-flops by serially shifting in/out one bit per clock cycle. (Loading a scan chain of 800 scan flip-flops requires 800 clock cycles.) Because such serial scan testing is relatively time consuming, many of those in the art have divided a design's scan flip-flops into numerous scan chains. Loading eight scan chains of 100 scan flip-flops each, requires 100 clock cycles as opposed to 800 clock cycles. The ATPG program is still run on the entire design; the resulting ATPG patterns are translated to support multiple scan chains. In other words, the scan patterns in both of the above scenarios, the more efficient approach just described and the basic approach, are generated on a chip-level basis. That is, the original ATPG pattern and its tools are applied to the full piece of integrated circuitry rather than to selected parts of the same.
New ATPG patterns are required whenever the logic changes, especially if scan flip-flops are added and deleted from the design. Moreover, generating compact, high coverage ATPG patterns often requires multiple runs with different tool constraints and options. The scan patterns developed from an ATPG arrangement also must be debugged. This debugging typically is a long process because of (not infrequent) mismatches between the circuit design's behavior and the ATPG tools zero-delay simulations.